1. Field of the Invention
The invention relates to a method for adjusting phase locked loop variables configuration having at least two frequency dividers with output signals that are compared in a phase detector.
2. Description of the Related Art
Such configurations are known, among other sources, from an article that was translated into English under the title "New CMOS phase locked loop Component for Use in Mobile Radios in the 900 MHz Range" by G. Krings, H. U. Irmer and R. Greiderer, which is a reprint from the article entitled "Nachrichtentechnische Zeitschrift [Communications Technology Journal] (1988), Vol. 41, No. 1, pp. 24-28, and from a commercially available integrated circuit TBB 206 and a spec book of the firm Siemens entitled "ICs for Radio Equipment 1989/90", pp. 51-72, and in particular page 71 in conjunction with page 54.
Pull-in processes occur in such configurations upon the first time that they are turned on and also when the frequency is changed, or in other words upon channel changing. During these pull-in processes, the configuration does not furnish the desired signal at its output. The magnitude of the pull-out state produced by the channel change is of significance for the next pull-in process, particularly upon channel changing from a locked-on state.
In the commercial circuit TBB 206, such a problem was counteracted by so-called synchronous programming (see page 61 of the aforementioned spec book). As a result, upon program-controlled changing of the divider ratios and therefore of the output frequency of the phase locked loop, the new frequency divider ratios are set while maintaining the phase difference existing at the programming time (at the moment of change). That is attained by buffer-storing the frequency divider ratios that have been serially written in and are to be varied in so-called shadow registers, and transferring the buffer-stored frequency divider ratios, once both shadow registers have been written and the next phase comparison has been performed in the phase detector, into the applicable data register of the corresponding frequency divider simultaneously, in such a way that both frequency dividers are set to the new frequency divider ratios at the instant of the next phase comparison. Even if only the frequency divider ratio of one frequency divider is varied, the takeover of the new frequency divider ratio takes place synchronously with the existing phase difference. The frequency dividers are typically constructed as counters with a data register, which count downward to zero to the value, which is the frequency divider ratio, contained in the data register, and then are reset to the value contained in the data register. Accordingly, once the frequency divider ratios of both frequency dividers that are to be newly set are present in the applicable shadow registers, then the two counters or frequency dividers, once they have each counted to zero, are reset, since the shadow register contents are transferred to the data registers of the frequency dividers.
In that known configuration, the output variables of two frequency dividers are compared in a phase detector. The output variable of the phase detector is passed on to a loop filter through an output stage, which in that case is a current source known as a charge pump. The output variable of the output stage can additionally be varied by means of a further variable, independently of the output variable of the phase detector. In the present case, the amplitude of the output current of a current source is controllable by means of a control current of a current mirror. By exerting influence on the additional variable which affects the output signal of the phase detector, a pull-in process can be advantageously varied. The output amplitude of the phase detector is variable in the known configuration by varying a data word, so that the output signal of the phase detector can be adapted to given requirements under program control.
Nevertheless, the course of the pull-in processes upon channel changing in such known configurations is not optimal, especially if the phase locked loop has not yet locked on. It is accordingly an object of the invention to provide a method of adjusting phase locked loop variables, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known methods of this general type and with which the pull-in processes, particularly upon channel changing, can be further optimized.